The present invention relates to a semiconductor device which includes a test circuit such as a BIST (built in self test) circuit for testing a memory, and to a technique which is useful for a system-on-chip type semiconductor device and further a system-in-package type semiconductor device mounting the system-on-chip type data processor chip and a memory chip.
The following publicly known documents are found out in the prior art investigation conducted after completion of the present invention. In Japanese Patent Laid-open No. 2006-138645, a semiconductor device having an operation mode in which a logic and a memory mounted on a single package are tested by the BIST circuit, is described. In Japanese Patent Laid-open No. 11-16393, a test circuit is described, which memorizes positional information of a failure in a semiconductor having a self-diagnosis circuit and a built-in memory when the failure is detected in the semiconductor, and compresses the information to output it. In Japanese Patent Laid-open No. 10-55694, in a test of a DRAM such as a galloping mode test, a technique is described, in which a plurality of times of the same address errors is compressed at a compression section to reduce writing frequency of fail data.